High-voltage gate driving circuits can be used in various fields, such as motor driving, electronic ballasts for fluorescent lamp, and power management, etc. The level shift circuit in a high-voltage gate driving circuit is a key component of the entire circuit, the electrical performance of high-voltage insulated gate field effect tube LDMOS elements constituting the level shift circuit and the electrical coupling between high-voltage LDMOS elements have influence on the performance of the level shift circuit, and the heavy current and high voltage of source electrode and drain electrode of the high-voltage LDMOS elements may cause a parasitic effect in other areas of the entire integrated circuit and thereby have influence on the electrical performance of the entire integrated circuit; therefore, the electrical performance of high-voltage LDMOS elements in a level shift circuit and the isolation of high-voltage LDMOS elements are undoubtedly important considerations in the research of performance and technique of high-voltage gate driving circuits. The design of isolation structures in high-voltage integrated circuits is always crucial in the design of high-voltage integrated circuits. However, withstand voltage and leak current are two major challenges in the design and technique of isolation structures. A high-voltage integrated circuit (HVIC) is a circuit that integrates new high-voltage power elements, high-voltage and low-voltage logic control circuits, and protection circuits in a single silicon chip. HVICs are of great significance for miniaturization, intellectualization, and power saving of the devices such as household electrical appliances and automobile electronics, owing to their advantages in system, such as high reliability, high stability, lower power consumption, small size, light weight, and low cost. A HVIC can be divided into high-side circuit, low-side circuit, and high-low junction terminal region. To prevent the impact of high-voltage circuit on nearby circuits, cross-impact between high-voltage power elements and high-voltage circuit, and crosstalk between elements, the isolation technology of a HVIC is the basis for normal and effective operation of the HVIC as well as a key component of a high-voltage/low-voltage compatible technical platform.
The isolation between high-voltage LDMOSs in level shift circuits is always the focus in the research of half-bridge driving circuits. A variety of isolation methods are used in existing half-bridge driving chips. Among these isolation methods, the most effective and the most prominent isolation method is the high-voltage LDMOS isolation method for high-voltage gate driving circuit mentioned in the U.S. Pat. No. 7,655,979 of Fairchild Semiconductor, wherein, the high-voltage gate driving circuit comprises a high-voltage (HV) region, a low-voltage (LV) region, and a HV-LV junction terminal region, the high-voltage LDMOS is located between the high-voltage region and the low-voltage region and employs partial junction terminal region as its drift region. The HV-LV junction terminal region and the low-voltage region, the high-voltage LDMOS and the high-voltage region/low-voltage region, and the high-voltage LDMOS and the HV-LV junction terminal region are isolated from each other with a p-n junction isolation structure composed of a P-type well and a P-type buried layer, i.e., around the entire high-voltage LDMOS, the high-voltage LDMOS is isolated from other parts of the circuit with a p-n junction isolation structure composed of a P-type well and a P-type buried layer, wherein, the p-n junction isolation is implemented with a P-type junction isolation composed of a P-type well on the epitaxial layer and a P-type buried layer below the P-type well and penetrating the epitaxial layer to the substrate; such a p-n junction isolation structure can isolate the high voltage LDMOS from other parts of the circuit nearby. However, when the high-voltage region is connected to high voltage, the P-type junction isolation region near the isolation part of high-voltage region can be depleted completely, while the P-type junction isolation region away from the isolation part of high-voltage region can't be depleted completely, resulting in a partial breakdown phenomenon. As a result, the withstand voltage of the entire isolation structure is decreased.